module detect_top(
    input clk,
    input rst,
    input strb,
    input [15:0] in_r,
    input [15:0] in_i,
    output find
    );
    
    parameter size=128, width = 16;//all parameters cannot be changed
    //state(main) ,S0 LOAD ,S1-S16 MULT OUT, S17-S23 OUT, S24--27 ADD , S28-29 ABS ,S30 Truncate ,S31-34 POWER ,S35-s36 compare,S37:WAIT
    //state(power),S0 IN->REG LAST->REG, S1-S6 MULT, S7:OUT, S8: ACC+IN*IN, S9:ACC - LAST*LAST, S10:WAIT
    parameter idle = 40'h00_0000_0000; 
    parameter s0  = 40'h00_0000_0001,s1= 40'h00_0000_0002,s2= 40'h00_0000_0004,s3= 40'h00_0000_0008,s4= 40'h00_0000_0010;
    parameter s5  = 40'h00_0000_0020,s6= 40'h00_0000_0040,s7= 40'h00_0000_0080,s8= 40'h00_0000_0100,s9= 40'h00_0000_0200;
    parameter s10 = 40'h00_0000_0400,s11=40'h00_0000_0800,s12=40'h00_0000_1000,s13=40'h00_0000_2000,s14=40'h00_0000_4000;
    parameter s15 = 40'h00_0000_8000,s16=40'h00_0001_0000,s17=40'h00_0002_0000,s18=40'h00_0004_0000,s19=40'h00_0008_0000;
    parameter s20 = 40'h00_0010_0000,s21=40'h00_0020_0000,s22=40'h00_0040_0000,s23=40'h00_0080_0000,s24=40'h00_0100_0000;
    parameter s25 = 40'h00_0200_0000,s26=40'h00_0400_0000,s27=40'h00_0800_0000,s28=40'h00_1000_0000,s29=40'h00_2000_0000;
    parameter s30 = 40'h00_4000_0000,s31=40'h00_8000_0000,s32=40'h01_0000_0000,s33=40'h02_0000_0000,s34=40'h04_0000_0000;
    parameter s35 = 40'h08_0000_0000,s36=40'h10_0000_0000,s37=40'h20_0000_0000,s38=40'h40_0000_0000;
    reg [39:0] state;  
      
    //rom,ZC_SEQ
    reg  [width-1:0]            zc_r[0:size-1];
    reg  [width-1:0]            zc_i[0:size-1];
    reg                         zc_fin;
    reg  [$clog2(size)+1:0]     addr_r;
    wire [$clog2(size):0]       addr;
    wire [width -1:0]           rom_out;
    wire                        zc_fin_w;
    
    zc_rom rom_0(addr, clk, rom_out);
    
    assign addr              = addr_r[$clog2(size):0];
    assign zc_fin_w          = zc_fin;
    integer i0;
    always @(posedge clk) begin
        if(rst) begin
            zc_fin<=1'b0;
            addr_r<='b0;
            zc_r[0]<='b0;
            zc_i[0]<='b0;
        end
        
        else if(addr_r <= (size+size)) begin
            zc_fin <= 1'b0;
            if((0 < addr_r )&( addr_r <= size))          zc_r[addr_r-1'b1] <= rom_out;
            if((size < addr_r) & (addr_r<= (size+size))) zc_i[addr_r-size-1'b1] <=rom_out;
            addr_r <= addr_r+1'b1;
            end
        else if(addr_r > (size+size))zc_fin <=1'b1;
    end
    
    //load
    reg [width-1:0] seq_r[0:size-1];
    reg [width-1:0] seq_i[0:size-1];
    integer i;
    always @(posedge clk) begin
        if(rst) begin
            for (i = 0 ; i< size ; i = i+1)
            begin
                seq_r [i] <=   'b0;
                seq_i [i] <=   'b0;
            end
        end
        else case(state)
            s0: begin
                seq_r[0]<=in_r;
                seq_i[0]<=in_i;
                for(i=size-1;i>0;i=i-1) begin
                    seq_r[i]<=seq_r[i-1];
                    seq_i[i]<=seq_i[i-1];
                end
            end
        endcase
    end
    
    //mult
    parameter m_len = 8, m_width=32;
    reg  [width-1:0] m_r_r    [0:m_len-1]; //input
    reg  [width-1:0] m_i_r    [0:m_len-1];
    reg  [width-1:0] m_zc_r_r [0:m_len-1]; //zc
    reg  [width-1:0] m_zc_i_r [0:m_len-1];
    wire [width-1:0] m_r      [0:m_len-1];
    wire [width-1:0] m_i      [0:m_len-1];
    wire [width-1:0] m_zc_r   [0:m_len-1];
    wire [width-1:0] m_zc_i   [0:m_len-1];
    wire [m_width-1:0] mo_r   [0:m_len-1];
    wire [m_width-1:0] mo_i   [0:m_len-1];
    
    generate
        genvar j,j1,j2;
        for (j=0;j<m_len;j=j+1) begin:mul
            mul_conj mul_ins(.clk(clk),.cal_en(zc_fin_w),
                .R(m_r[j]),.I(m_i[j]),
                .sR(m_zc_r[j]),.sI(m_zc_i[j]),
                .z(mo_r[j]),.zi(mo_i[j]),.rdy()
                );
            assign m_r[j] = m_r_r[j];
            assign m_i[j] = m_i_r[j];
            assign m_zc_r[j] = m_zc_r_r[j];
            assign m_zc_i[j] = m_zc_i_r[j];
        end
    endgenerate
    
    integer i1;
    always @(posedge clk) begin
        if(rst) begin
            for(i1=0;i1<m_len;i1=i1+1) begin
                m_r_r[i1]<= 'b0;
                m_i_r[i1]<= 'b0;
                m_zc_r_r[i1]<= 'b0;
                m_zc_i_r[i1]<= 'b0;
            end
        end
        else case(state)
            s1:begin
                for(i1=0;i1<m_len;i1=i1+1) begin
                    m_r_r[i1]<= seq_r[i1];
                    m_i_r[i1]<= seq_i[i1];
                    m_zc_r_r[i1]<= zc_r[size-1-i1];
                    m_zc_i_r[i1]<= zc_i[size-1-i1];
                end
            end
            s2:begin
                for(i1=0;i1<m_len;i1=i1+1) begin
                    m_r_r[i1]<= seq_r[i1+m_len];
                    m_i_r[i1]<= seq_i[i1+m_len];
                    m_zc_r_r[i1]<= zc_r[size-1-(i1+m_len)];
                    m_zc_i_r[i1]<= zc_i[size-1-(i1+m_len)];
                end
            end
            s3:begin
                for(i1=0;i1<m_len;i1=i1+1) begin
                    m_r_r[i1]<= seq_r[i1+m_len*2];
                    m_i_r[i1]<= seq_i[i1+m_len*2];
                    m_zc_r_r[i1]<= zc_r[size-1-(i1+m_len*2)];
                    m_zc_i_r[i1]<= zc_i[size-1-(i1+m_len*2)];
                end
            end
            s4:begin
                for(i1=0;i1<m_len;i1=i1+1) begin
                    m_r_r[i1]<= seq_r[i1+m_len*3];
                    m_i_r[i1]<= seq_i[i1+m_len*3];
                    m_zc_r_r[i1]<= zc_r[size-1-(i1+m_len*3)];
                    m_zc_i_r[i1]<= zc_i[size-1-(i1+m_len*3)];
                end
            end
            s5:begin
                for(i1=0;i1<m_len;i1=i1+1) begin
                    m_r_r[i1]<= seq_r[i1+m_len*4];
                    m_i_r[i1]<= seq_i[i1+m_len*4];
                    m_zc_r_r[i1]<= zc_r[size-1-(i1+m_len*4)];
                    m_zc_i_r[i1]<= zc_i[size-1-(i1+m_len*4)];
                end
            end
            s6:begin
                for(i1=0;i1<m_len;i1=i1+1) begin
                    m_r_r[i1]<= seq_r[i1+m_len*5];
                    m_i_r[i1]<= seq_i[i1+m_len*5];
                    m_zc_r_r[i1]<= zc_r[size-1-(i1+m_len*5)];
                    m_zc_i_r[i1]<= zc_i[size-1-(i1+m_len*5)];
                end
            end
            s7:begin
                for(i1=0;i1<m_len;i1=i1+1) begin
                    m_r_r[i1]<= seq_r[i1+m_len*6];
                    m_i_r[i1]<= seq_i[i1+m_len*6];
                    m_zc_r_r[i1]<= zc_r[size-1-(i1+m_len*6)];
                    m_zc_i_r[i1]<= zc_i[size-1-(i1+m_len*6)];
                end
            end
            s8:begin
                for(i1=0;i1<m_len;i1=i1+1) begin
                    m_r_r[i1]<= seq_r[i1+m_len*7];
                    m_i_r[i1]<= seq_i[i1+m_len*7];
                    m_zc_r_r[i1]<= zc_r[size-1-(i1+m_len*7)];
                    m_zc_i_r[i1]<= zc_i[size-1-(i1+m_len*7)];
                end
            end
            s9:begin
                for(i1=0;i1<m_len;i1=i1+1) begin
                    m_r_r[i1]<= seq_r[i1+m_len*8];
                    m_i_r[i1]<= seq_i[i1+m_len*8];
                    m_zc_r_r[i1]<= zc_r[size-1-(i1+m_len*8)];
                    m_zc_i_r[i1]<= zc_i[size-1-(i1+m_len*8)];
                end
            end
            s10:begin
                for(i1=0;i1<m_len;i1=i1+1) begin
                    m_r_r[i1]<= seq_r[i1+m_len*9];
                    m_i_r[i1]<= seq_i[i1+m_len*9];
                    m_zc_r_r[i1]<= zc_r[size-1-(i1+m_len*9)];
                    m_zc_i_r[i1]<= zc_i[size-1-(i1+m_len*9)];
                end
            end
            s11:begin
                for(i1=0;i1<m_len;i1=i1+1) begin
                    m_r_r[i1]<= seq_r[i1+m_len*10];
                    m_i_r[i1]<= seq_i[i1+m_len*10];
                    m_zc_r_r[i1]<= zc_r[size-1-(i1+m_len*10)];
                    m_zc_i_r[i1]<= zc_i[size-1-(i1+m_len*10)];
                end
            end
            s12:begin
                for(i1=0;i1<m_len;i1=i1+1) begin
                    m_r_r[i1]<= seq_r[i1+m_len*11];
                    m_i_r[i1]<= seq_i[i1+m_len*11];
                    m_zc_r_r[i1]<= zc_r[size-1-(i1+m_len*11)];
                    m_zc_i_r[i1]<= zc_i[size-1-(i1+m_len*11)];
                end
            end
            s13:begin
                for(i1=0;i1<m_len;i1=i1+1) begin
                    m_r_r[i1]<= seq_r[i1+m_len*12];
                    m_i_r[i1]<= seq_i[i1+m_len*12];
                    m_zc_r_r[i1]<= zc_r[size-1-(i1+m_len*12)];
                    m_zc_i_r[i1]<= zc_i[size-1-(i1+m_len*12)];
                end
            end
            s14:begin
                for(i1=0;i1<m_len;i1=i1+1) begin
                    m_r_r[i1]<= seq_r[i1+m_len*13];
                    m_i_r[i1]<= seq_i[i1+m_len*13];
                    m_zc_r_r[i1]<= zc_r[size-1-(i1+m_len*13)];
                    m_zc_i_r[i1]<= zc_i[size-1-(i1+m_len*13)];
                end
            end
            s15:begin
                for(i1=0;i1<m_len;i1=i1+1) begin
                    m_r_r[i1]<= seq_r[i1+m_len*14];
                    m_i_r[i1]<= seq_i[i1+m_len*14];
                    m_zc_r_r[i1]<= zc_r[size-1-(i1+m_len*14)];
                    m_zc_i_r[i1]<= zc_i[size-1-(i1+m_len*14)];
                end
            end  
            s16:begin
                for(i1=0;i1<m_len;i1=i1+1) begin
                    m_r_r[i1]<= seq_r[i1+m_len*15];
                    m_i_r[i1]<= seq_i[i1+m_len*15];
                    m_zc_r_r[i1]<= zc_r[size-1-(i1+m_len*15)];
                    m_zc_i_r[i1]<= zc_i[size-1-(i1+m_len*15)];
                end
            end             
        endcase
    end
    
    //OUT
    reg [m_width-1:0] mo_r_r [0:size-1]; //output
    reg [m_width-1:0] mo_i_r [0:size-1];
    integer i2;
    always @(posedge clk) begin
        if(rst) begin
            for(i2=0;i2<size;i2=i2+1) begin
                mo_r_r[i2] <= 'b0;
                mo_i_r[i2] <= 'b0;
                
            end
        end
        else case(state)
            s8:begin
                for(i2=0;i2<m_len;i2=i2+1) begin
                    mo_r_r[i2]<= mo_r[i2];
                    mo_i_r[i2]<= mo_i[i2];
                end
            end
            s9:begin
                for(i2=0;i2<m_len;i2=i2+1) begin
                    mo_r_r[i2+m_len]<= mo_r[i2];
                    mo_i_r[i2+m_len]<= mo_i[i2];
                end
            end
            s10:begin                          
                for(i2=0;i2<m_len;i2=i2+1) begin
                    mo_r_r[i2+m_len*2]<= mo_r[i2];    
                    mo_i_r[i2+m_len*2]<= mo_i[i2];    
                end                           
            end                               
            s11:begin                          
                for(i2=0;i2<m_len;i2=i2+1) begin
                    mo_r_r[i2+m_len*3]<= mo_r[i2];    
                    mo_i_r[i2+m_len*3]<= mo_i[i2];    
                end                           
            end                               
            s12:begin                          
                for(i2=0;i2<m_len;i2=i2+1) begin
                    mo_r_r[i2+m_len*4]<= mo_r[i2];    
                    mo_i_r[i2+m_len*4]<= mo_i[i2];    
                end                           
            end                               
            s13:begin                          
                for(i2=0;i2<m_len;i2=i2+1) begin
                    mo_r_r[i2+m_len*5]<= mo_r[i2];    
                    mo_i_r[i2+m_len*5]<= mo_i[i2];    
                end                          
            end                               
            s14:begin                          
                for(i2=0;i2<m_len;i2=i2+1) begin
                    mo_r_r[i2+m_len*6]<= mo_r[i2];    
                    mo_i_r[i2+m_len*6]<= mo_i[i2];    
                end                           
            end                               
            s15:begin                          
                for(i2=0;i2<m_len;i2=i2+1) begin
                    mo_r_r[i2+m_len*7]<= mo_r[i2];    
                    mo_i_r[i2+m_len*7]<= mo_i[i2];    
                end                           
            end                               
            s16:begin                          
                for(i2=0;i2<m_len;i2=i2+1) begin
                    mo_r_r[i2+m_len*8]<= mo_r[i2];    
                    mo_i_r[i2+m_len*8]<= mo_i[i2];    
                end                           
            end                               
            s17:begin                          
                for(i2=0;i2<m_len;i2=i2+1) begin
                    mo_r_r[i2+m_len*9]<= mo_r[i2];    
                    mo_i_r[i2+m_len*9]<= mo_i[i2];    
                end                           
            end                               
            s18:begin                          
                for(i2=0;i2<m_len;i2=i2+1) begin
                    mo_r_r[i2+m_len*10]<= mo_r[i2];    
                    mo_i_r[i2+m_len*10]<= mo_i[i2];    
                end                           
            end
            s19:begin                          
                for(i2=0;i2<m_len;i2=i2+1) begin
                    mo_r_r[i2+m_len*11]<= mo_r[i2];    
                    mo_i_r[i2+m_len*11]<= mo_i[i2];    
                end                           
            end                      
            s20:begin                          
                for(i2=0;i2<m_len;i2=i2+1) begin
                    mo_r_r[i2+m_len*12]<= mo_r[i2];    
                    mo_i_r[i2+m_len*12]<= mo_i[i2];    
                end                           
            end                               
            s21:begin                          
                for(i2=0;i2<m_len;i2=i2+1) begin
                    mo_r_r[i2+m_len*13]<= mo_r[i2];    
                    mo_i_r[i2+m_len*13]<= mo_i[i2];    
                end                           
            end                               
            s22:begin                          
                for(i2=0;i2<m_len;i2=i2+1) begin
                    mo_r_r[i2+m_len*14]<= mo_r[i2];    
                    mo_i_r[i2+m_len*14]<= mo_i[i2];    
                end                           
            end                               
            s23:begin                          
                for(i2=0;i2<m_len;i2=i2+1) begin
                    mo_r_r[i2+m_len*15]<= mo_r[i2];    
                    mo_i_r[i2+m_len*15]<= mo_i[i2];    
                end                           
            end                                                                       
        endcase
    end
    
    //ADD S24--S27
    parameter a1_width = 34,a2_width = 36 , a3_width = 38,a4_width = 39,num1= 32,num2 = 8;
    reg signed [a1_width-1:0] add_1_r [0:num1-1];
    reg signed [a1_width-1:0] add_1_i [0:num1-1];
    reg signed [a2_width-1:0] add_2_r [0:num2-1];
    reg signed [a2_width-1:0] add_2_i [0:num2-1];
    reg signed [a3_width-1:0] add_3_r;
    reg signed [a3_width-1:0] add_3_i;
    reg signed [a3_width-1:0] add_4_r;
    reg signed [a3_width-1:0] add_4_i;
    reg signed [a4_width-1:0] add_5_r;
    reg signed [a4_width-1:0] add_5_i;
    integer i3,i4;
    always @(posedge clk) begin
        if(rst)begin
            for(i3=0;i3<num1;i3=i3+1) begin
                add_1_r[i3] <='b0;
                add_1_i[i3] <='b0;
            end
            for(i4=0;i4<num2;i4=i4+1) begin
                add_2_r[i4] <='b0;
                add_2_i[i4] <='b0;
            end
            add_3_r<='b0;
            add_3_i<='b0;
            add_4_r<='b0;
            add_4_i<='b0;
            add_5_r<='b0;
            add_5_i<='b0;
        end
        else case(state)
            s24: begin
                for(i3=0;i3<num1;i3=i3+1) begin
                    add_1_r[i3] <= $signed(mo_r_r[i3*4])+$signed(mo_r_r[i3*4+1])+$signed(mo_r_r[i3*4+2])+$signed(mo_r_r[i3*4+3]);
                    add_1_i[i3] <= $signed(mo_i_r[i3*4])+$signed(mo_i_r[i3*4+1])+$signed(mo_i_r[i3*4+2])+$signed(mo_i_r[i3*4+3]);
                end
            end
            s25: begin
                for(i3=0;i3<num2;i3=i3+1) begin
                    add_2_r[i3] <= add_1_r[i3*4]+add_1_r[i3*4+1]+add_1_r[i3*4+2]+add_1_r[i3*4+3];
                    add_2_i[i3] <= add_1_i[i3*4]+add_1_i[i3*4+1]+add_1_i[i3*4+2]+add_1_i[i3*4+3];
                end
            end
            s26:begin
                add_3_r<=add_2_r[0]+add_2_r[1]+add_2_r[2]+add_2_r[3];
                add_3_i<=add_2_i[0]+add_2_i[1]+add_2_i[2]+add_2_i[3];
                add_4_r<=add_2_r[4]+add_2_r[5]+add_2_r[6]+add_2_r[7];
                add_4_i<=add_2_i[4]+add_2_i[5]+add_2_i[6]+add_2_i[7];
            end
            s27:begin
                add_5_r<=add_3_r+add_4_r;
                add_5_i<=add_3_i+add_4_i;
            end
        endcase
    end
    
    //Truncate S28,29
    reg [a4_width-1:0] z_abs_r_r;
    reg [a4_width-1:0] z_abs_i_r;

    wire [a4_width-1:0] z_abs_r;
    wire [a4_width-1:0] z_abs_i;
    assign z_abs_r = $unsigned(add_5_r);
    assign z_abs_i = $unsigned(add_5_i);
    always @(posedge clk) begin
        if(rst) begin
            z_abs_r_r<='b0;
            z_abs_i_r<='b0;

        end
        else case(state)
            s28:begin
                z_abs_r_r <= z_abs_r[a4_width-1]?(~z_abs_r+1'b1):z_abs_r;
                z_abs_i_r <= z_abs_i[a4_width-1]?(~z_abs_i+1'b1):z_abs_i;
            end
        endcase
    end

    
    reg  [a4_width-16:0]     result_w_tru_re_r;
    reg  [a4_width-16:0]     result_w_tru_im_r;
    wire [a4_width-16:0]     result_w_tru_re;
    wire [a4_width-16:0]     result_w_tru_im;

    assign result_w_tru_re = result_w_tru_re_r; //carry
    assign result_w_tru_im = result_w_tru_im_r;
    always @(posedge clk)begin
        if(rst) begin
            result_w_tru_re_r <= 'b0;
            result_w_tru_im_r <= 'b0;
        end
        else case(state)
            s29: begin
                result_w_tru_re_r <= {z_abs_r_r[a4_width-1],z_abs_r_r[a4_width-2:16],(z_abs_r_r[15] | z_abs_r_r[14])};
                result_w_tru_im_r <= {z_abs_i_r[a4_width-1],z_abs_i_r[a4_width-2:16],(z_abs_i_r[15] | z_abs_i_r[14])};
            end
        endcase
    end


    //ABS TIMES ABS S30-S33 (24X24)
    wire [(a4_width-16+1)*2-1:0]   result_pwr_w_re;
    wire [(a4_width-16+1)*2-1:0]   result_pwr_w_im;
    mult_25x25 mult_abs_power_re (.CLK(clk), .A(result_w_tru_re), .B(result_w_tru_re), .P(result_pwr_w_re));
    mult_25x25 mult_abs_power_im (.CLK(clk), .A(result_w_tru_im), .B(result_w_tru_im), .P(result_pwr_w_im));

    //POWER LOAD S0
    reg  [width - 1 : 0]   power_in_re_r;
    reg  [width - 1 : 0]   power_in_im_r;
    reg  [width - 1 : 0]   power_last_re_r;
    reg  [width - 1 : 0]   power_last_im_r;
    wire [width - 1 : 0]   power_in_re_w;
    wire [width - 1 : 0]   power_in_im_w;
    wire [width - 1 : 0]   power_last_re_w;
    wire [width - 1 : 0]   power_last_im_w;
    assign power_in_re_w   = power_in_re_r;
    assign power_in_im_w   = power_in_im_r;
    assign power_last_re_w = power_last_re_r;
    assign power_last_im_w = power_last_im_r;

    always @(posedge clk) begin
        if(rst) begin
            power_in_re_r    <=  'b0;
            power_in_im_r    <=  'b0;
            power_last_re_r  <=  'b0;
            power_last_im_r  <=  'b0;
        end
        else case(state)
            s0:begin
                power_in_re_r   <=      in_r;
                power_in_im_r   <=      in_i;
                power_last_re_r <=      seq_r[size-1];
                power_last_im_r <=      seq_i[size-1];
            end
        endcase
    end

    //POWER MULT S1-S6
    wire [width*2-1:0]      power_inxin_w;
    wire [width*2-1:0]      power_lastxlast_w;
    
    mul_conj mul_inxin(.clk(clk),.cal_en(zc_fin_w),
        .R(power_in_re_w),.I(power_in_im_w),
        .sR(power_in_re_w),.sI(power_in_im_w),
        .z(power_inxin_w),.zi(),.rdy()
    );
    mul_conj mul_lastxlast(.clk(clk),.cal_en(zc_fin_w),
        .R(power_last_re_w),.I(power_last_im_w),
        .sR(power_last_re_w),.sI(power_last_im_w),
        .z(power_lastxlast_w),.zi(),.rdy()
    );

    //POWER ADD S7 S8
    parameter power_width_gap = $clog2(size);
    reg  [width*2+$clog2(size)-1:0] power_acc;
    reg  [width*2+$clog2(size)-1:0]              power_lastxlast_neg_r;
    always @(posedge clk) begin
        if(rst) begin
            power_acc                   <= 'b0;
            power_lastxlast_neg_r       <= 'b0;
        end
        else case(state)
            idle: power_acc           <='b0;
            s7: begin
                power_acc             <= power_acc + {{power_width_gap{1'b0}},power_inxin_w};
                power_lastxlast_neg_r <= (~{{power_width_gap{1'b0}},power_lastxlast_w}) + 1'b1;
            end
            s8: power_acc             <= power_acc + power_lastxlast_neg_r;  
        endcase
    end

    //POWER SHIFT S9
    parameter width_gap = (a4_width-16+1)*2+1 - (width*2+$clog2(size));
    reg  [width_gap+width*2+$clog2(size)-1:0] power_acc_shift_r;
    always @(posedge clk) begin
        if(rst) power_acc_shift_r <= 'b0;
        else case(state)
            s9: power_acc_shift_r <= {{width_gap{1'b0}},power_acc};//({{width_gap{1'b0}},power_acc} << 4) - ({{width_gap{1'b0}},power_acc} << 1); // coe
        endcase
    end


    

    //GET PWR_XCORR S34-35
    reg [(a4_width-16+1)*2-1:0] result_pwr_re_r;
    reg [(a4_width-16+1)*2-1:0] result_pwr_im_r;
    reg [(a4_width-16+1)*2:0]   result_pwr_r;
    always @(posedge clk) begin
        if(rst) begin
            result_pwr_re_r <= 'b0;
            result_pwr_im_r <= 'b0;
            result_pwr_r    <= 'b0;
        end
        else case(state)
            s34: begin
                result_pwr_re_r <= result_pwr_w_re;
                result_pwr_im_r <= result_pwr_w_im;
            end
            s35: begin
                result_pwr_r    <= {1'b0,result_pwr_re_r} + {1'b0,result_pwr_im_r};
            end
        endcase
    end

    //COMPARE S36-37
    //parameter thre = 40'h00_1000_0000;
    
    reg [1:0] cpr_hi_r;
    reg cpr_lo_r;
    reg find_r;
    assign find = find_r;
    always @(posedge clk) begin
        if(rst) begin
            find_r<=1'b0;
            cpr_hi_r<='b0;
            cpr_lo_r<='b0;
        end
        else case(state)
            s36: begin
                cpr_hi_r[1] <= (result_pwr_r[(a4_width-16+1)*2  :  (a4_width-16+1)] >    power_acc_shift_r[(a4_width-16+1)*2  :  (a4_width-16+1)])?1'b1:1'b0;
                cpr_hi_r[0] <= (result_pwr_r[(a4_width-16+1)*2  :  (a4_width-16+1)] ==   power_acc_shift_r[(a4_width-16+1)*2  :  (a4_width-16+1)])?1'b1:1'b0;
                cpr_lo_r    <= (result_pwr_r[(a4_width-16+1)-1:0]                   >    power_acc_shift_r[(a4_width-16+1)-1:0])?1'b1:1'b0;
            end
            s37: find_r <= cpr_hi_r[1] ? 1'b1: (cpr_hi_r[0] ? cpr_lo_r : 1'b0);
        endcase
    end
    
    /*
    //WAIT
    reg [6:0] cnt;
    always @(posedge clk) begin
        if(rst) cnt<='b0;
        else case(state) 
            s37: cnt<=cnt+1'b1;
            default:cnt<='b0;
        endcase
    end
    */
    
    // STATE MACHINE
    always @(posedge clk) begin
        if(rst) state<=idle;
        else case(state)
            idle: state<= zc_fin? s0:idle;
            s0:  state<= state<<1;
            s1:  state<= state<<1;
            s2:  state<= state<<1;
            s3:  state<= state<<1;
            s4:  state<= state<<1;
            s5:  state<= state<<1;
            s6:  state<= state<<1;
            s7:  state<= state<<1;
            s8:  state<= state<<1;
            s9:  state<= state<<1;
            s10:  state<= state<<1;
            s11:  state<= state<<1;
            s12:  state<= state<<1;
            s13:  state<= state<<1;
            s14:  state<= state<<1;
            s15:  state<= state<<1;
            s16:  state<= state<<1;
            s17:  state<= state<<1;
            s18:  state<= state<<1;
            s19:  state<= state<<1;
            s20:  state<= state<<1;
            s21:  state<= state<<1;
            s22:  state<= state<<1;
            s23:  state<= state<<1;
            s24:  state<= state<<1;
            s25:  state<= state<<1;
            s26:  state<= state<<1;
            s27:  state<= state<<1;
            s28:  state<= state<<1;
            s29:  state<= state<<1;
            s30:  state<= state<<1;
            s31:  state<= state<<1;
            s32:  state<= state<<1;
            s33:  state<= state<<1;
            s34:  state<= state<<1;
            s35:  state<= state<<1;
            s36:  state<= state<<1;
            s37:  state<= state<<1;
            s38:  state<= (strb)?s0:s38;
            //s37: state<= (cnt==7'd58)?s0:s37;
            default: state<= idle;
        endcase
    end
endmodule